1. Field of the Invention
The present invention relates generally to a delay circuit for delaying an applied signal by a prescribed time period, and more particularly to a delay circuit for use in generation of an internal control signal in a semiconductor memory device.
2. Description of the Background Art
In recent years, the integration density of a semiconductor integrated circuit has tremendously increased. As the integration density increases, the number of transistors integrated per one chip increases for the same chip area, and therefore scaling down of transistors has inevitably advanced in order to reduce the transistor size. As the scaling down of the transistor proceeds, power supply voltage Vcc is reduced from for example 5V to 3.3V in order to secure the reliability of the insulating film of an MOS transistor (an insulating gate type field effect transistor). Meanwhile, although the number of transistors thus increases, in order to keep current in a chip (semiconductor integrated circuit device) in a stand-by state from increasing, and to keep current consumption when the semiconductor integrated circuit device is in a stand-by state as small as possible the absolute value Vth of the threshold voltage of the MOS transistor may not be smaller than a certain value.
FIG. 12 is a graph showing the relation between the drain current Ids and the gate-source voltage Vgs of an n channel MOS transistor. The threshold voltage of an MOS transistor is defined as gate-source voltage Vgs upon flowing of a certain drain current Ids. If, therefore, the threshold voltage Vth2 of the n channel MOS transistor is reduced to threshold voltage Vth1, curve I-V indicating the correlation between the drain current and the gate-source voltage transits from curve I to curve II. In this case, for the gate-source voltage Vgs of the n channel MOS transistor of 0V, current I1 flows in curve II and the current I1 is larger than current I2 in curve I. Currents I1 and I2 are usually referred to as "subthreshold current". For a p channel MOS transistor, inversion of the sign of gate-source voltage Vgs provides a curve indicating the relation between the drain current and the gate-source voltage.
As illustrated in FIG. 12, the stand-by current of the MOS transistor, in other words the subthreshold current decreases as the absolute value Vth of threshold voltage increases. If the absolute value of gate-source voltage Vgs is higher than the absolute value of the threshold voltage, a large drain current Ids abruptly passes through the MOS transistor. Therefore, based on the relation between the high speed operation ability of the MOS transistor by the current driving capability and the stand-by current according to subthreshold current, the absolute value Vth of the threshold voltage of about 0.6V is usually used.
ON current at the time of the conduction of the MOS transistor (current in a saturated state) is determined by the difference between power supply voltage Vcc and the absolute value of threshold voltage, in other words by Vcc-Vth. If Vcc=3.3V and Vth=0.6V, Vcc-Vth=2.7V holds. For the voltage value of power supply voltage Vcc, a deviation of .+-.10%V from the rated voltage is tolerated. Therefore, for a semiconductor integrated circuit with Vcc of 3.3V, the lower limit of power supply voltage Vcc=3.0V, and the upper limit Vcc=3.6V. In this case, the difference between power supply voltage Vcc and the absolute value Vth of threshold voltage, Vcc-Vth has a deviation of about 25% from 2.4V to 3.0V. The current driving capability of the MOS transistor, in other words drain current Ids which may be supplied by the transistor is approximately in proportion to the square of Vcc-Vth. More specifically, the drain current Ids of the MOS transistor in a saturated region is given by: EQU Ids=.beta.(Vgs-Vth).sup.2 .about..beta.(Vcc-Vth ).sup.2
wherein, the relation represented by .vertline.Vds.vertline..gtoreq..vertline.Vds-Vth.vertline. is established in the saturated region. Vds indicates the drain-source voltage of the MOS transistor. .beta. is constant parameter determined by factors such as the material of a gate insulating film used in the MOS transistor and the ratio of channel width W to channel length L.
Therefore, in use under rated voltage, if Vcc-Vth deviates in the range of 20%, the current driving capability of the MOS transistor deviates in the range of about 55% (1.25.sup.2 =1.56). A description follows on how the deviations of power supply voltage Vcc and the absolute value Vth of threshold voltage influence, the design of a semiconductor integrated circuit. In the following description, a dynamic random access memory (DRAM) will be discussed as an example of semiconductor integrated circuit devices.
FIG. 13 is a diagram schematically showing the configuration of a memory cell array portion in the DRAM. In FIG. 3, a memory cell MC is provided corresponding to a crossing portion of a word line WL and a bit line BL. Memory cells MC are arranged in a matrix of rows and columns, word line WL is connected with a row of memory cells, and bit line BL is connected with memory cells corresponding to a column. Usually in the "folded bit line pair" configuration, bit lines BL and /BL are provided in pairs. When memory cell data is determined, one of bit line BL and /BL provides reference voltage. Memory cell MC includes a capacitor Cm for storing information in an electric charge form, and an n channel MOS transistor (access transistor) Tm conducting in response to the signal potential of word line WL and connecting capacitor Cm to bit line BL.
A sense amplifier SA provided for bit line BL senses and amplifies data held by memory cell MC which is read out on bit line BL. Sense amplifier SA is activated in response to a sense amplifier activation signal .phi.SA, and differentially amplifies the potential relative to that of bit line /BL (not shown) which is complementary to bit line BL. Bit line BL has parasitic resistance Rp and parasitic capacitance Cp by the interconnection.
FIG. 14 is a waveform chart representing the operation of the sense amplifier in FIG. 13. Referring to FIG. 14, the operation of reading data from a memory cell will be described.
When a memory cycle starts, a row selection operation is executed according to an applied address signal, the potential of word line WL corresponding to the addressed row rises, and word line WL attains a selected state. In response to the rising of the potential of word line WL, access transistor Tm in memory cell MC conducts, and capacitor Cm is connected to bit line BL. Now, consider that bit line BL (and /BL) is precharged to an intermediate potential Vcc/2, and that capacitor Cm stores an "H" level. In this case, positive charge moves from capacitor Cm to bit line BL, thus raising the potential of bit line BL. The potential of bit line BL is transferred to sense amplifier SA through parasitic resistance Rp and parasitic capacitance Cp. The sense node of sense amplifier SA therefore gradually rises according to time constant Rp.multidot.Cp which is given by resistance Rp and parasitic capacitance Cp. If the potential of sense node (bit line BL) of sense amplifier SA increases enough, sense amplifier activation signal .phi.SA is activated, and sense amplifier SA amplifies the potential of bit line BL (the potential of sense node).
In order to assure that sense amplifier SA senses and amplifies the storage information of memory cell MC, voltage (readout voltage) read out on bit line BL (sense node) must be large enough, and therefore a sufficient time period must be secured until sense amplifier activation signal .phi.SA is activated since the rising of the potential of word line WL.
FIG. 15A is a diagram schematically showing the configuration of a sense amplifier activation signal generation portion. In FIG. 15A, the sense amplifier activation signal generation portion includes four stages of cascaded inverters IV1, IV2, IV3 and IV4 receiving an internal row address strobe signal RAS. Inverters IV2 to IV4 are each provided with a delaying capacitor at each input portion. More specifically, for inverter IV2, capacitors C1 and C2 are connected in series between power supply potential node Vcc and ground node, for inverter IV3, capacitors C3 and C4 are connected in series between power supply node Vcc and ground node, and to the input portion of inverter IV4, capacitors C5 and C6 are connected in series between power supply node Vcc and ground node. Capacitors C1, C3 and C5 connected to power supply node Vcc each have the function of delaying the falling of a signal, and capacitors C2, C4 and C6 connected to the ground node each has the function of delaying the rising of a signal. Necessary delay is given by time required for charging/discharging the capacitors. FIG. 15A arrangement includes another configuration in which word line driving signal .phi.WL is generated from internal row address strobe signal RAS through inverter IV1, capacitors C1 and C2, and inverter IV2.
FIG. 15B is a waveform chart representing the operation of the sense amplifier activation signal generation portion shown in FIG. 15A. If row address strobe signal RAS rises from an inactive L level to an active H level, the output signal of inverter IV1 responsively falls from an H level to an L level. In this case, time required for discharging capacitor C1 makes the change of the signal gradual, and the potential of the input portion of inverter IV2 falls gradually enough as compared to internal row address strobe signal RAS. If the signal potential of the input portion of inverter IV2 becomes lower than the input logical threshold value of inverter IV2, the output signal of inverter IV2 rises from an L level to an H level. (The time required for charging capacitor C4 is indicated in broken line in FIG. 15B.) The operation is executed also in inverters IV3 and IV4, rendering each signal change to be gradual and sense amplifier activation signal .phi.SA output from inverter IV4 attains an H level active state after passage of the total delay time of inverters IV1 to IV4 and delay time given by the time required for charging/discharging capacitors C1 to C6. Relatively large delay time can be provided in a small occupied area, taking advantage of charging/discharging of capacitors.
FIG. 16A is a diagram showing the configuration of an inverter by way of illustration. In FIG. 16A, an inverter IV includes a p channel MOS transistor PT connected between power supply node Vcc and an output node and receiving an input signal IN at its gate, and an n channel MOS transistor NT connected between the output node and the ground node and receiving input signal IN at its gate. For inverter IV formed of the CMOS transistor, the operation speed changes in response to the voltage level of power supply voltage Vcc. This is because the voltage level of input signal IN applied to the gate changes in response to the level of power supply voltage Vcc. In an unsaturated region, the drain-source voltage Vds affects the drain current.
As described above, the current driving capability of the MOS transistor is approximately in proportion to the square of Vcc-Vth. Therefore, as the voltage level of power supply voltage Vcc rises, the driving capability increases, and therefore the speed of the change of an output signal OUT increases as illustrated in FIG. 16B. If therefore sufficient delay time is secured for the upper limit of power supply voltage Vcc, the change speed of signal decreases for the lower limit of power supply voltage Vcc, and therefore the delay time becomes too long, thus delaying an activation timing for the sense amplifier accordingly, and prolonging accessing time.
For example, consider that 2 ns are secured as delay time for the upper limit of Vcc=3.6V. In this case, for the lower limit of Vcc=3.0V, the current driving capability of the MOS transistor forming the inverter decreases by about 55%. If therefore an increase of charge/discharge amount by 25% for the capacitor at the upper limit of power supply voltage is taken into account, the delay time increases by about 25% (1.56/1.25=1.25) to be about 2.5 ns. Therefore, the extra delay time of 0.5 ns result in increase in accessing time through the delay of the sense amplifier activation timing, and the performance of the semiconductor memory device is degraded as a result.
In order to reduce the dependence of the delay time on power supply voltage as described above, a delay circuit as shown in FIG. 17A has been used. In FIG. 17A, the delay circuit includes a first inverter formed of MOS transistors PT1 and NT1, and a second inverter formed of MOS transistors PT2 and NT2. A resistor element R is connected between the source of p channel MOS transistor PT1 of the first inverter and power supply node Vcc. A capacitor C is connected between an intermediate node MN between the output node of the first inverter and the input node of the second inverter and the ground node. FIG. 17B is a waveform chart representing the operation of the delay circuit shown in FIG. 17A.
As shown in FIG. 17B, when input IN falls from an H level to an L level, p channel MOS transistor PT1 conducts, and current flows to intermediate node MN through resistor element R and MOS transistor PT1. Capacitor C is provided between intermediate node MN and the ground node. Therefore, the potential of intermediate node MN gradually rises in the speed determined by the time constant R.multidot.C of resistor element R and capacitor C. If the potential of intermediate node MN exceeds the input logical threshold value of the second inverter (MOS transistors PT2 and NT2), output signal OUT falls from an H level to an L level.
Since the potential rising speed of intermediate node MN is determined by time constant R.multidot.C and does not depend on power supply voltage Vcc, delay time for input signal IN corresponding to output signal OUT does not differ between the upper limit and the lower limit of Vcc. Therefore, even if the power supply voltage fluctuates, a necessary internal control signal (such as sense amplifier activation signal) can be activated with a prescribed delay time period.
In the delay circuit shown in FIG. 17A, if input signal IN rises from an L level to an H level, MOS transistor NT1 conducts, thereby discharging stored charges in capacitor C at a high speed.
As a configuration similar to that shown in FIG. 17A, resistor element R may be connected between the drain of p channel MOS transistor PT1 and the output node, or resistor element R may be connected to the source or drain of n channel MOS transistor NT1. However, the position to connect resistor element R may appropriately be determined depending on which one of the rising and falling of the input signal is delayed.
The input logical threshold value of the CMOS inverter may be given as follows: EQU Vith=Vthn/Vcc+.sqroot..beta.p/.beta.N(1-.vertline.Vthp.vertline./Vcc)/1+.sq root..beta.p/.beta.N.multidot.Vcc (1)
wherein Vthn and Vthp are threshold voltages of n channel MOS transistor and p channel MOS transistor, respectively, and .beta.N and .beta.p are transfer factors of n channel MOS transistor and p channel MOS transistor, respectively. The input logical threshold value Vith is usually fixed at the voltage level of Vcc/2. The input logical threshold value Vith therefore changes in response to change in power supply voltage Vcc, the threshold voltage of the MOS transistor, and change in the transfer factor .beta. due to variations in the manufacturing parameters. If input logical threshold value Vith slightly changes, the delay time changes greatly for the configuration of the delay circuit shown in FIG. 17A. The change in the delay time will be described in conjunction with FIG. 18.
As illustrated in FIG. 18, if the logical threshold value of the second inverter (MOS transistors PT2 and NT2) is (A), output signal OUT changes at time tA. Meanwhile, if the logical threshold value of the second inverter (MOS transistors PT2 and NT2) is (B), in other words lowered, the output signal OUT changes at time tB earlier than time tA. The potential change of intermediate node MN is gradual. Therefore, a slight change in the logical threshold value increases time difference between tA and tB, thus greatly changing the delay time. If the delay time changes, the timing for activating the internal control signal (such as sense amplifier activation signal) of the semiconductor memory device greatly changes, the internal operation timing shift largely, and it would be difficult to secure stable operations. Particularly in the case of the sense amplifier activation signal, an access time for accessing the semiconductor memory device greatly changes.
In a DRAM, many internal control signals are generated by delaying row address strobe signal RAS, in other words a memory cell selection operation initiation instruction signal, besides the sense amplifier activation signal, and the timing for internal operations (operations associated with row selection operation) is greatly shifted. As a result, and therefore it would be difficult to secure stable operation.
Along with the semiconductor memory device, generally in semiconductor integrated circuit devices, various signals are generated by delaying a certain signal. For example, such various signals are produced by generating a one shot pulse when a signal changes, by processing a certain signal and further processing the result of processing with the original signal, and by delaying the original signal until the processing result signal is ascertained. In any of the cases, the delay circuit preferably provides fixed delay time irrespectively of fluctuation in power supply voltage Vcc and input logical threshold value in succeeding stages.